1. Field of the Invention
The present invention relates to stack package structures and fabrication methods thereof, and, more particularly, to a stack package structure having copper pillars and a fabrication method thereof.
2. Description of Related Art
Along with the miniaturization of electronic products, less area is available on packaging substrates for disposing semiconductor chips or package structures. Accordingly, vertical stacking technologies have been developed to provide stack package structures. A plurality of solder balls are disposed on a package structure so as for another package structure to be stacked thereon, thus forming a package-on-package (PoP) structure that meets the requirement of high component density on a small bonding area.
FIGS. 1A to 1E are schematic cross-sectional views showing a conventional stack package structure and a fabrication method thereof.
Referring to FIG. 1A, a substrate 10 is provided. A surface 101 of the substrate 10 has a plurality of die attach pads 11 and a plurality of conductive pads 12 disposed around the die attach pads 11. An insulating layer 13 is formed on the surface 101 of the substrate 10 and has a plurality of openings 130 for exposing the die attach pads 11 and the conductive pads 12. A plurality of first solder balls 14 are disposed on the die attach pads 11.
Referring to FIG. 1B, a semiconductor chip 15 is disposed on the first solder balls 14.
Referring to FIG. 1C, an encapsulant 16 is formed on the substrate 10 to encapsulate the semiconductor chip 15.
Referring to FIG. 1D, a plurality of second solder balls 17 are disposed on the conductive pads 12.
Referring to FIG. 1E, a package structure 18 is disposed on the second solder balls 17, thus forming a PoP package structure.
In the above-described PoP package structure, the second solder balls 17 on the conductive pads 12 must have a large size so as to prevent the package structure 18 from coming into contact with the semiconductor chip 15. The large-size solder balls occupy much area of the substrate and increase the thickness of the overall package structure, thereby adversely affecting the miniaturization of electronic products.
Therefore, there is a need to provide a stack package structure and a fabrication method thereof so as to overcome the above-described drawbacks.